“Single-Chip versatile signal generator suitable for navigation” (SING) is an ESA project kicked off in July 2022 and will be concluded by January 2024.
The objective of SING project is to design a single-chip solution for a versatile signal generator suitable for satellite navigation payloads. Such a design should be flexible enough to generate the main GNSS signals and modulations schemes.
Currently, such flexibility can only be achieved using Field Programmable Gate Arrays (FPGAs) with an external digital-to-analog convertor (DAC) to generate the RF signal. The high data rates in FPGA transceivers and the external DAC implies an increased power consumption in comparison with other non-flexible solutions.
The proposed solution by the consortium is based on the latest generations of radio frequency System on chips (RFSoCs), which provides high flexibility and internal DACs in a single chip and significantly reduces power consumption.
The SING consortium offers a solution based on a team that has extensive experience with the key technologies and areas relevant to this project. The consortium consists of GMV in the UK and Spain as well as the Gdańsk University of Technology (GUT).
The team of GMV in UK is leading the project and mainly responsible for the design of the system, meanwhile GMV’s team in Spain main responsibility is the physical implementation of the system and GUT’s main responsibility is the system verification and testing.